[ntp:hackers] [Gpsd-dev] A lightweight synchronization mechanism for shared memory
terje at tmsw.no
Fri Mar 25 18:20:53 UTC 2011
Gary E. Miller wrote:
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> Yo dave!
> On Fri, 25 Mar 2011, Dave Hart wrote:
>> My recollection is that MIPS R4000, Alpha, or both do not support
>> byte-wide access, instead emitting load aligned destination word into
>> register, twiddle the byte into the register, then store aligned
>> destination word. By "word" I mean unsigned int, essentially, or
>> possibly 32-bit on 64-bit processors.
> Having actually programmed MIPS and Alpha I can comfirm this misfeature.
> It was a PITA to work around.
The original Alpha had this PITA feature, by the time of the '164 they
had to add 8 and 16-bit load/store ops.
The main problem was in the drivers for memory-mapped interfaces with 8
or 16-bit read/write registers, the workaround was supposed to be a
special set of (aliased) memory-mapped pages where a 32-bit access would
in fact only touch 8 or 16 bits.
Anyway, using 32-bit accesses exclusively is much safer.
- <Terje at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
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