[ntp:questions] TAC-2 internal delay

test test at iinet.net.au
Sat Oct 18 11:38:08 UTC 2003


I'm currently setting up a TAC-2 and Oncore VP based reference clock
for connection to a FreeBSD server's serial port and am trying fine
tune the accuracy of the 1PPS signal as much as possible.  Working out
antenna and measurement cable delays was fairly easy, but the TAC-2
operations manual contains the following text:

"Note: This screen also shows a value of 8 nsec for the
internal receiver delay. This is a provisional value subject
to more detailed calibrations of the TAC and is based on
the propagation delay thru two 74AC14 gates."

Looking at the TAC-2 schematic, the 1PPS signal from the GPS module
gets to the DCD serial pin via one 74AC04 and one MAX232.  The
datasheets I have for these chips give their propagation delays as 8ns
for the 74AC04 and 1.3us for the transmit section of the MAX232.

So, the question I have is about the relevance of the 8ns receiver
delay.  Shouldn't it be closer to 1.3us, or am I just missing the
point completely?


More information about the questions mailing list