[ntp:questions] Re: TAC-2 internal delay

Paul Croome Paul.Croome at softwareag.com
Tue Oct 21 07:50:04 UTC 2003


test <test at iinet.net.au> wrote in message news:<ge92pv0ta14fj5u9o7djco6pp4ga5jl9tg at 4ax.com>...
> 
> "Note: This screen also shows a value of 8 nsec for the
> internal receiver delay. This is a provisional value subject
> to more detailed calibrations of the TAC and is based on
> the propagation delay thru two 74AC14 gates."

The signal path from the GPS module to either of the low-Z PPS outputs
or the 'extender' output does indeed go through two inverters; this must the
figure to which this paragraph is referring.

> 
> Looking at the TAC-2 schematic, the 1PPS signal from the GPS module
> gets to the DCD serial pin via one 74AC04 and one MAX232.  The
> datasheets I have for these chips give their propagation delays as 8ns
> for the 74AC04 and 1.3us for the transmit section of the MAX232.
> 

Right. From the GPS module to the RS232 output, the PPS goes through an
inverter and the RS232 driver.

Does anybody know the numbers for a typical UART receiver? I'm guessing
that the input circuitry of the computer will contribute another microsecond
or so of delay...

Paul



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