[ntp:questions] micro-optimization

Augustine evandro at mailinator.com
Wed Mar 11 20:21:07 UTC 2009

On Mar 11, 4:19 am, Terje Mathisen <"terje.mathisen at tmsw.no">
> I do know that Intel intends to make processor-based timers more useful
> by setting up a counter which always runs at a fixed rate, independent
> of any frequency power stepping. On such a cpu RDTSC would again be the
> best choice, but hopefully the OS would realize this and start to use it
> for QPC.

What both Intel and AMD did on Core2 and Phenom was to move the "TSC"
over to the BU.  Therefore, RDTSC latency grew to typically 60 to 100
cycles with, and this is worse for NTP, jitter, because of the
different clock domains involved.


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