[ntp:questions] A proposal to use NIC launch time support to improve NTP
jwalck at netnod.se
Thu Dec 20 08:08:19 UTC 2012
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On 12/19/2012 11:52 PM, Brian Utterback wrote:
> On 12/19/12 16:49, Brian Utterback wrote:
>> Generally, the PPS signal does not go over the PCI bus. The
>> kernel gets its PPS signal via the serial port. You would
>> therefore like the controller to have its own PPS signal input,
>> but I don't see one in the datasheet.
>> So you are back to worrying about the sync of the kernel clock
>> and the controller clock. It might not matter too much, but it
>> will kind of depend on how the receive timestamp is obtained from
>> the card. The receive timestamp and transmit timestamp have got
>> to be on the same time source or you could run into problems.
> Actually, the controller does have the equivalent of a PPS input.
> There is a provision for detecting a level change on a single input
> line. The controller timestamp of the level change is stored in a
> register. The driver can read the register and if it knows what the
> timestamp should have been when that signal came in, it can
> calculate the offset. There is then a register that it can write
> the offset to, which results in the controller adjusting its clock
> by that amount.
> There is also a facility in the controller to generate a periodic
> clock based signal. Pretty nifty all told, if the driver makes use
> of it.
Yes, you found it before I had a chance to add here. Nifty is a good
work to describe this.:)
Not only can you do a one-shot adjustment, but you can control the
ns-fraction added at each 8ns tick of the clock using (I hope I
remember the name correctly now) TIMINCA to steer and lock the clock
to the PPS.
The benefit compared to a serial line-connected PPS is of course the
lack of a interrupt to read the time register so there should be less
jitter in this reading.
Generating a PPS output from a second SDP (more or less a GPIO pin)
for tracability will give you a clue for how good the whole scheme
works in the end.
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