[ntp:questions] A proposal to use NIC launch time support to improve NTP
dennis.c.ferguson at gmail.com
Thu Dec 20 18:21:52 UTC 2012
On 19 Dec, 2012, at 13:49 , Brian Utterback <brian.utterback at oracle.com> wrote:
> On 12/19/12 14:05, unruh wrote:
>> On 2012-12-19, Hal Murray<hal-usenet at ip-64-139-1-69.sjc.megapath.net> wrote:
>>> Doesn't the PPS signal to the kernel have to go over the same PCI bus?
> Generally, the PPS signal does not go over the PCI bus. The kernel gets its PPS signal via the serial port. You would therefore like the controller to have its own PPS signal input, but I don't see one in the datasheet.
The interrupt from the serial port is transmitted across some bus
(often by message signalling these days), and it seems to me that
a PCIe-attached serial port is probably one of the better situations
you could hope for now. The "legacy I/O" peripherals on many Intel/AMD
motherboards, including the serial ports, are instead often attached
to the processor support chipset via an LPC bus connection and the
latter, being designed as an economical replacement for the ISA bus,
is just dead slow.
Hardware PPS sampling, and synchonising pairs of internal clocks with
PIO operations, is much, much better than anything involving interrupts.
> So you are back to worrying about the sync of the kernel clock and the controller clock. It might not matter too much, but it will kind of depend on how the receive timestamp is obtained from the card. The receive timestamp and transmit timestamp have got to be on the same time source or you could run into problems.
The size of the problem with multiple time sources is limited by the
precision with which one clock can be synchronised with another. With
a good arrangement for sampling those clocks against each other this
problem can be minuscule compared to NTP's requirements.
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